Minimize ringing of the boost converter switch node
Problem Description
The circuit diagram in Figure 1 (Boost Power Supply) illustrates the critical loop of a boost converter, which includes parasitic inductance and capacitance. The inductor is labeled as LPAR (parasitic inductance), and the capacitor is labeled as CPAR (parasitic capacitance). The point where the two switches meet the inductor is known as the switching node. These parasitic elements often lead to mutual inductance, causing voltage oscillations on the switching node that can exceed 200 MHz. If the amplitude of this ringing exceeds the absolute maximum voltage rating of the low-side switch, it may cause damage. Additionally, conducted radiation or electromagnetic interference (EMI) from the ringing can interfere with nearby ICs.
Figure 2 displays the measured waveform of the switching node with a time scale of 5 ns/div. The oscilloscope and probe used have a bandwidth of at least 500 MHz, which is about twice the estimated 200 MHz ringing frequency. To minimize ground loop effects and ensure accurate measurements, the probe’s ground loop was kept as short as possible. With VIN = 3.3 V and VOUT = 5 V, the expected peak voltage on the switching node should be around 5.7 V (VOUT + VDIODE). However, the measured peak voltage of the ringing reaches 9.8 V, which could potentially damage the low-side switch.
Designers have several options to reduce ringing. When using a controller, selecting FETs and diodes with minimal parasitic capacitance is crucial. Shortening the distance between the switches and inductors through careful PCB layout helps minimize LPAR2 and LPAR3. Reducing the distance between the FET’s power supply pin and the ground plane minimizes LPAR1. Placing the output capacitor close to the diode’s cathode and the power ground reduces LPAR4 and LPAR5. A high-frequency bypass capacitor (COUT-BYP) between the output and ground, typically ranging from 0.01 mF to 2.2 mF, also helps suppress ringing.
However, due to board size constraints or integrated FET power ICs, improving layout may not always be feasible. In such cases, a snubber circuit consisting of RSNUB and CSNUB connected from the switch node to the power ground is necessary. The snubber absorbs energy during switch transitions, reducing voltage spikes caused by parasitic inductance. It provides an alternate current path, thereby minimizing voltage transients and subsequent ringing on the parasitic capacitance.
This application report discusses how to select the right snubber values to suppress ringing without significantly affecting the switch turn-off rise time or overall efficiency.
After determining the initial ringing frequency (fINIT = 217 MHz) based on the total parasitic inductance [LΣPAR#] and total parasitic capacitance [CΣPAR#], adding an appropriate capacitor [CADD] between the switch node and ground reduces the ringing frequency to half. As shown in Figure 3, adding a 300 pF capacitor lowers the frequency to 113 MHz.
The resonant frequency of the LC circuit is inversely proportional to the square root of the product of inductance and capacitance. Adding CADD increases the total capacitance to four times its original value, meaning CΣPAR# = CADD/3. This represents the minimum required capacitance for CSNUB. The total parasitic inductance causing the ringing can be calculated as follows:
Once determined, the optimal snubber resistance is the characteristic impedance of the original parasitic capacitance [CΣPAR# = 100 pF] and inductance [LΣPAR# = 5.4 nH]:
From Equation 3, RSNUB is approximately 7.3Ω, so rounding up to 10Ω is practical. Set CSNUB to 330 pF, slightly higher than the calculated value. Connect this to the switch node and ground. The resulting waveform, shown in Figure 4, demonstrates that the ringing has been significantly reduced. The peak voltage dropped from 9.8 V to 8 V, a reduction of 1.8 V or about 20%, with only a 2 ns increase in switching time.
Designers can increase CSNUB further until the transition becomes distorted, indicating effective damping. However, larger CSNUB values increase energy absorption, leading to higher power loss in RSNUB. The power loss can be calculated using PSNUB = 1/2 × CSNUB × VPK² × fSW, where VPK is the reduced peak voltage and fSW is the switching frequency. Engineers must ensure that RSNUB is rated to handle this power. Generally, choosing a standard value greater than CADD/2 ensures a 20% reduction in peak voltage with minimal efficiency loss.
Similar techniques are used online to suppress ringing in the secondary diode of flyback converters. The approach is similar but tailored for different topologies.
Using RC Snubbers to Reduce Ringing in Flyback Converters’ Secondary Diode
In summary, this method has been proven effective in reducing or eliminating ringing. Engineers should prioritize controlling the power source during design to avoid excessive losses. Key steps include:
1. Select MOSFETs or diodes with low parasitic capacitance.
2. Shorten the critical loop during PCB layout to minimize parasitic effects.
3. Consider the RC snubber method only if the acceptable power loss or heat dissipation is within limits.
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