Minimize ringing on the boost converter switch node
Understanding the Problem
The circuit diagram in Figure 1 (Boost Power Supply) illustrates the critical loop of a boost converter, which includes parasitic inductance and capacitance. The inductor is labeled as LPAR (parasitic inductance), and the capacitor is labeled as CPAR (parasitic capacitance). The point where the two switches meet the inductor is known as the switching node. These parasitic elements often create oscillations at frequencies above 200 MHz. If the amplitude of this ringing exceeds the maximum voltage rating of the low-side switch, it can lead to damage. Additionally, the electromagnetic interference (EMI) or conducted radiation caused by this ringing may affect nearby integrated circuits (ICs).
Figure 2 shows the measured waveform of the switching node with a time scale of 5 ns/div. The oscilloscope and probe used have a bandwidth of at least 500 MHz, which is about twice the estimated 200 MHz ringing frequency. To avoid distortion from inductive pickup, the ground loop of the probe was minimized. With VIN = 3.3 V and VOUT = 5 V, the expected peak voltage at the switching node should not exceed VOUT + VDIODE ≈ 5.7 V. However, the measured peak voltage of the ringing is 9.8 V, which could potentially damage the low-side switch.
Designers have several options to reduce ringing in power supply designs. When using a controller, it’s advisable to select FETs and diodes with minimal parasitic capacitance. Shortening the distance between the switches and inductors through careful PCB routing can help minimize LPAR2 and LPAR3. Reducing the distance between the FET's power pin and the ground plane minimizes LPAR1. Placing the large output capacitor close to the diode cathode and ground also helps reduce LPAR4 and LPAR5. Adding a high-frequency bypass capacitor (COUT-BYP) between the output and ground, typically in the range of 0.01 mF to 2.2 mF, further suppresses ringing.
However, due to board size constraints or internal parasitics in integrated FET power ICs, improving routing may not always be feasible. In such cases, a snubber circuit composed of RSNUB and CSNUB is necessary. This circuit provides an alternative path for current when the switch closes, helping to dampen voltage spikes caused by parasitic inductance. It effectively reduces the ringing that occurs on the parasitic capacitance.
This application report outlines how to determine the optimal values for the snubber components to suppress ringing without significantly affecting the switch turn-off rise time or reducing overall efficiency.
After determining the ringing frequency (fINIT = 217 MHz) based on the total parasitic inductance [LΣPAR#] and total parasitic capacitance [CΣPAR#], adding an appropriate capacitor [CADD] between the switch node and ground can reduce the ringing frequency by half. As shown in Figure 3, adding a 300 pF capacitor lowers the frequency to 113 MHz.
The resonant frequency of an LC circuit is inversely proportional to the square root of the product of inductance and capacitance. By increasing the total capacitance to four times its original value (CΣPAR# + CADD = 4 × CΣPAR#), we ensure that CADD is at least one-third of the original parasitic capacitance. This gives us the minimum required value for CSNUB. The total parasitic inductance causing the ringing can then be calculated as follows:
Once this is done, the optimal snubber resistance is determined by the characteristic impedance of the original parasitic capacitance [CΣPAR# = CADD/3 = 100 pF] and the stray inductance [LΣPAR# = 5.4 nH]:
From Equation 3, RSNUB is approximately 7.3Ω, and rounding up gives 10Ω. Setting CSNUB to 330 pF, which is greater than the calculated CADD, and RSNUB to 10Ω connected to ground, results in a significant reduction in ringing. As shown in Figure 4, the peak amplitude is reduced from 9.8 V to 8 V, a 20% decrease, with only a 2 ns increase in transition time.
Designers can increase CSNUB until the transition node begins to bend (Q = 1), indicating effective suppression. However, increasing CSNUB also increases energy loss, leading to higher power consumption in RSNUB. The power dissipation in the snubber can be calculated as PSNUB = ½ × CSNUB × VPK² × fSW, where VPK is the reduced peak voltage and fSW is the switching frequency. Designers must ensure that the RSNUB package can handle this power. Typically, the next standard value for CSNUB should be chosen to halve the oscillation frequency, allowing a 20% reduction in peak amplitude while keeping efficiency loss minimal.
Similar techniques are used online to suppress ringing in the secondary diode of flyback converters. The approach is similar but tailored to the specific configuration of the flyback topology.
Using RC to Suppress Ringing in Flyback Secondary Diodes
In conclusion, this method has been proven effective in reducing or eliminating ringing. Engineers should prioritize minimizing parasitic effects during the design phase, as excessive absorption can lead to significant losses. Key recommendations include:
1. Choose MOSFETs or diodes with minimal parasitic capacitance.
2. During PCB layout, shorten the length of the oscillating loop as much as possible.
3. When applying the RC snubber method, ensure that the trade-off between performance loss and heat dissipation is acceptable.
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