Jim Anderson, senior vice president and general manager of the Network Solutions Group at LSI, wrote on the Web World website that Moore's Law is not enough to keep up with the explosive growth of data traffic. The pace of fast network speed demand. Therefore, there is a need for smarter chips and software methods.
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One of the best ways to speed up mobile and data center networks is to combine general-purpose processors with smart chip accelerator engines to dramatically optimize byte-priority and optimize network performance and cloud-based services.
One of the fundamental challenges facing the industry is the data flow gap: the gap between network and storage capacity requirements by 30% to 50% per year and the IT budget growing by 5% to 7% per year. The growth of cloud-based service applications and the consumption of data storage are driving the growth of data traffic between the network and the cloud. As data traffic grows far beyond the growth of infrastructure that supports it, network operators face significant pressure to find smarter ways to improve performance.
The cloud data center was built using existing technology and has so far successfully improved performance through brute force. The so-called brute force is to increase the hardware of servers, switches, processor cores and memory. However, this approach is costly and non-sustainable, increasing hardware cost and floor space as well as cooling and power requirements, and is far from solving the problem of network latency.
Adding intelligence in a smart chip approach optimizes the processing of packets transmitted over mobile networks and data center networks. In particular, smart chips enable next-generation networks to understand the criticality of data, then operate in an optimized manner, prioritize data and route data, thereby reducing overall traffic and accelerating the transfer of important digital information, such as voice and video. Real-time data.
Intelligent network
Universal processors that increasingly use multiple cores are widely used in network infrastructure. These processors drive switches and routers, firewalls and load balancers, WAN accelerators, and VPN (Virtual Private Network) gateways. However, these systems are not fast enough to keep up with the speed of their own data streams. The underlying reason is that general-purpose processors are designed to be dedicated to compute-centric server-level workloads, not to handle network-centric workloads in current and next-generation infrastructure.
However, smart chips can accelerate the throughput of real-time workloads, such as high-performance packet processing while maintaining the constant performance of changing communication traffic demands.
Smart chips typically configure multiple cores of a general-purpose processor and are configured with multiple acceleration engines for communication network functions, such as packet classification for deep packet inspection, security processing, and traffic management. Some acceleration engines are powerful enough to perform dedicated packet processing tasks offloaded from general purpose processors, enabling them to complete switching, routing, and other network tasks in the FastPath Accelerator, dramatically improving network performance. Unload computationally intensive workloads to speed up the acceleration engine optimized for a specific workload. This approach can provide a huge advantage in the performance per watt of a general purpose processor.
Customized smart chips can be a good choice for network equipment vendors who want to build unique competitive advantages by integrating their own optimizations. For example, vendor-specific, differentiated smart assets can be integrated into the chip to provide advantages over general-purpose processors, including optimized baseband processing, deep packet inspection, and traffic management. This level of integration requires close collaboration between network devices and semiconductor vendors.
Future data center networks need to be faster and flatter, so they are smarter than ever. One of the key challenges to overcome in a virtualized large data center is the scalability of the console. To achieve a cloud-scale data center, the console needs to be scaled up or down. With a traditional scale-up approach, deploying additional or more powerful compute engines, acceleration engines, or both devices helps improve the performance of the network console.
In an emerging scaled-down architecture, such as a software-defined network, the console is separate from the data plane and typically runs on a standard server. In a scaled up or down architecture, an intelligent multicore communications processor that combines a general purpose processor with a dedicated hardware acceleration engine can significantly improve console performance. Some features, such as packet processing and traffic management, can usually be offloaded to a general-purpose communications processor that configures line cards.
While the efficiency of publishing this control and data plane is still an open issue, the obvious thing is that software-defined networks require smart chips to deliver the scalability performance they promise.
Intelligent storage
Smart chips for storage also help eliminate data flow gaps. Storage I/O bottlenecks exist between traditional hard disk and actuator arms and the speed limit for transferring data from hard disk media, as evidenced by the memory (100 nanoseconds) and the best hard disk (10 milliseconds) I/O (input/output) delays are 5 orders of magnitude apart.
Another limitation is that the amount of memory that can be supported by a traditional cache system (measured in GB) is only a small fraction of a hard disk capacity (measured in terabytes). These two products do not provide room for improved performance, but add a few gigabytes of DRAM memory or more faster hard drives to the cache device.
On the other hand, solid-state storage provided by NAND flash memory can effectively eliminate this bottleneck and provide high-speed I/O similar to memory in the same capacity as hard disk. In this regard, smart chips offer advanced wear-leveling, garbage collection and unique data reduction techniques to improve flash endurance and enhance error correction algorithms for RAID-style data protection. As shown, flash helps to eliminate the gap between capacity and latency between DRAM memory and hard disk.
Solid-state storage generally provides the highest level of performance when the flash cache accelerator card is installed directly on the server PCIe bus. Embedded or host-based smart caching software is used to place "hot data" in flash memory, where it is processed at 20 microseconds. This is 140 times faster than the 2800 milliseconds of the best-in-class hard drive. Some of these types of cards support multi-terabyte SSD storage. The current new class of solutions also provides internal flash and SAS (serial SCSI) interfaces to combine high-performance SSDs with RAID hard drive storage. A PCIe-based flash accelerator card can increase database application-level performance by 5 to 10 times in DAS (Direct Attached Storage) and SAN (Storage Area Network) environments.
Smart chips are at the heart of these solutions. Therefore, without a deep understanding of the views of semiconductor manufacturers, system vendors have no hope of eliminating the gap in data flow.
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