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Compared with the acquisition of ordinary video signals, the acquisition of CCD image data is characterized by high data transmission rate and many transmission channels. At present, the general CCD image data acquisition method is to insert a high-speed data acquisition card into the computer, and the data transmission between the acquisition card and the CCD camera through a point-to-point physical layer interface (such as RS-422, RS-485), the high-speed data acquisition card receives The data is written into the computer memory through the PCI bus, and then the data storage function of the capture card is used to write the data to the computer hard disk through the IDE interface. Although this method is simple and reliable, the collection of multi-channel and high-speed image data has certain limitations in data transmission and storage, which easily causes the loss of data frames, and the number of transmission lines increases as the number of transmission channels increases. Power consumption and noise also increase. Universal Serial Bus USB solves these problems well, with easy connection, no external power supply, plug and play, hot swappable, high bandwidth, low power, low cost, dynamic loading driver, cascading star The unique advantages of the topology expansion of the number of peripherals, simple, fast, two-way, reliable connection and communication between the host and the data acquisition system.1 hardware design
System design should be characterized by stability, flexibility, and versatility. Stability means not only ensuring undistorted transmission of data, but also ensuring that data is continuously lost without frame loss. Flexibility is reflected in the system's signal input path, system storage capacity, disk connection, etc. Modular and reconfigurable, the system can be used for other high-speed video image acquisition with a little workaround. The versatility is reflected in the system's ability to adapt to multiple channels and different rates of CCD image data acquisition, which requires the system to achieve channel merging and a wider data transmission band.
The hardware structure of the USB data acquisition system is shown in Figure 1.
The analog signal output by the sensor is strobed into the signal amplifier via a multi-way switch. The signal amplifier can automatically adjust the gain, and the input signal is amplified in the range of the A/D converter, and then controlled by the ARM chip. /D conversion, and then the converted digital signal is sent to the embedded microcontroller, which is transmitted to the PC for data processing by the USB interface circuit, and the control signal sent by the client application of the PC terminal is transmitted to the ARM chip through the USB interface. As the core data acquisition system.
1.1 Scheme selection
1.1.1 Selection of USB interface chip and main controller chip
There are two types of USB controllers, one is a single-chip integrated USB interface, such as Cypress's EZ-USB (based on 8051) series chips CY7C68013, CY7C64613, etc.; the other is a separate USB controller, such as Philips PDIUSBD12, ISP1581, NetChip's NET2888, National's USBN9603, USBN9604, etc. Although the former chip is simple to program, it needs to purchase a special development system, the investment is large, and the performance of the single chip is limited; the latter is characterized by low price, convenient connection and high reliability, but it does not have a CPU on the chip, and must be selected for micro processing. For protocol processing and data exchange. This system selects the cost-effective USB2.0 control chip ISP1581 without CPU on the chip, it is fully compliant with the USB 2.0 specification, and the speed can reach 480Mbps. The ISP1581 can quickly develop high-performance USB2.0 devices. At the same time, in order to meet the speed requirements, the main controller chip selects the high-performance, low-power ARM chip S3C44B0X.
1.1.2 Selection of signal amplification circuit and A/D conversion chip
In the high-speed data acquisition system, the field input signal is a high-frequency analog signal with a large variation range. If a single gain amplification is used, the amplitude of the amplified signal may exceed the range of the A/D conversion, so it must be based on the signal. changes to adjust the gain of the amplifier. This system selects the AD8321 frequency band, low noise, gain can be numerically controlled, and is very suitable for high frequency analog signal conditioning chip for preamplification in data acquisition system. High-frequency analog signal after amplification to the analog to digital converter, although S3C44B0X itself has eight 10-bit the ADC, but its internal integrated A / D converter analog input signals only 0 ~ 100Hz, and no sample and hold circuit and therefore it needs to be expanded. In order to meet the 8-channel acquisition, the high-speed A/D conversion chip AD7829 is selected, the maximum conversion rate is 2MSPS, and the conversion time is 420ns.
1.2 hardware interface circuit
The system hardware interface circuit is connected as shown in FIG.
The system uses the PD S3C44B0X port for bidirectional expansion port, connecting the AD7829 CONVST S3C44B0X with the PD1, for generating a switching pulse; AD7829 is connected to the EOC and S3C44B0X PD0, for generating an end of conversion signal. After the acquisition signal is converted by A/D, the data is first stored in the register of S3C44B0X. S3C44B0X sends the control signal first and then sends the data to ISP1581. Here, the buffer of ISP1581 is defined as 8 and 8 converted data are respectively written. . The PC is connected to the ISP1581 through the USB interface. The ISP1581 is responsible for classifying and interpreting the signals sent by the PC. The specific operation flow is as follows: the data sent by the PC to the USB device is written into the cache of the ISP1581 in the form of a packet, when the cache is written. After the full or data transmission is completed, the ISP1581 sends an interrupt signal to the ARM, and the ARM responds to the interrupt signal and enters the interrupt service routine to perform the corresponding packet processing. On the other hand, the USB device cannot actively send data to the host. Only when the PC requires the USB device to send data, the ARM writes the data required by the host to the cache of the corresponding endpoint of the ISP1581.
The data acquisition is performed by the PD port of S3C44B0X as the conversion pulse CONVST of AD7829. When the conversion of AD7829 is finished, the EOC output is active low level. After S3C44B0X is connected to the active level, the next address is sent, and then the data is read. When the sum signal of AD7829 is valid, the data of the next channel is input while the data is being read into the data buffer of S3C44B0X, so that 8 analog inputs are cyclically collected until the data acquisition ends. The flow chart of this process is shown in Figure 3. .
2.2 USB part software design
The USB system software consists of a firmware program, a USB system driver, and an application program.
2.2.1 Development of firmware programs
Firmware is actually placed inside the microcontroller program files, hardware to assist completion of the communication task. The INT interrupt signal of ISP1581 is connected to the EINT0 interrupt port of the microcontroller S3C44B0X. When receiving data or transmitting data successfully, an interrupt will be generated. The task of the firmware program is to respond to these interrupts, complete the configuration of the device, and let the USB driver Know the capabilities of the device, receive data from the USB host controller and send data to the host. The device firmware program is the core of the device operation, and the system is written with Keil C. The SP1581 firmware program is modular in design, including the main loop program, interrupt service program, USB standard request processing and bulk data transfer request processing. The structure of the firmware module is shown in Figure 4.
2.2.2 Application
Applications include Win32DLL programs and user applications. The Win32 Dynamic Link Library contains binary files for shared function libraries that can be used simultaneously by multiple applications. The client application is a software program that implements the functions of the data acquisition system, and is written in Visual C++ in this system.
2.2.3 USB System Driver
The USB system driver uses a hierarchical structure model (WDM), which defines a layered driver. The USB device driver does not directly talk to the hardware, but submits the USB request block to the bus driver through the USB driver interface. Complete hardware operation. From a system perspective, after the USB device is plugged into the host, the host detects the USB device, reads the device descriptor, and then the host enables the corresponding USB device driver according to the vendor ID and product ID provided in the device descriptor, and reads Take the configuration descriptor, interface descriptor, and endpoint descriptor in the USB device, and select the appropriate configuration, interface, and endpoint as needed to determine the transport mode. After this process is completed, data transfer between the PC and the USB device is possible.
The USB bus features make it ideal for use as a communication interface between a small instrument and a host, enabling a simple, fast, and reliable connection between the host and the portable instrument. Applying the USB interface to the data acquisition system improves the speed of the data acquisition system and enhances the system's anti-jamming capability and data transmission reliability. This paper introduces the software and hardware design and development scheme of the data acquisition system based on ARM chip S3C44B0X and USB2.0 interface control chip ISP1581 in detail. The design and development process is more complicated, involving the joint use of various software programs and hardware circuits. , the effect is good.
references
[1] Luo Hao, Yang Xiaofei. Design of Offline Data Acquisition System[J]. Microcomputer Information, 2006, 22(4): 93-95.
[2] Gao Meizhen, Hong Jiaping. Data Acquisition System Based on USB Interface and Embedded Chip Bus[J]. Instrument Technology and Sensors, 2005, (8): 51-53.
[3] Xing Wei, Liu Kaihua. Design of USB2.0 interface for data acquisition system[J].Electronic Measurement Technology,2006,29(1):12-13.
[4] Xia Yimin, Wang Guangjun. High-speed data acquisition system based on USB bus[J]. Foreign Electronic Components, 2003, (10): 20-23
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Model
NF-Y602
NF-Y702
NF-Y802
Size
length×width×height(mm)
2900×1360×1500
3430×1590×2300
Weight
(Kg)
1700
2200
Minimum Ground Clearance
(mm)
260
410
Engine
Model
3G25TC
YD4CZ70C1
YD4SZ80C1
Form
Electronic
injection.vertical.water-cooled.four-stroke
Rated power(kW)
44.1
51.5
58.8
Fuel
Diesel
Rated power(r/min)
2400
Starting method
Electric start
Steering Brake System
Steerig system type
Planetary differential steering
Brake system type
Wet friction steering
Drive Train
Clutch type
Single-chip single-acting
Transmission type
2(mechanical file)+2×2(hydraulic stepless speed change)
Transmission shift model
Gear shift
Walking System
Rack form
Rigid frame type
Track pitch section×number×width
90×46×280
90×50×350
The theoretical speed of each file(km/h)
Forward:mechanical block:4.86; 8.65
Hydraulic block:0-5.75; 0-10.24
Back:0-5.75;0-10.24
Working Device
Lifter type
Semi-split
Tillage depth control
Force adjustment
PTO form
Type1,non-independent
Power output shaft speed(r/min)
624/960
Model
NF-702
NF-802
NF-902
Size
length×width×height(mm)
3690×1500×2400
3690×1650×2560
Weight
(Kg)
2255
2450
Minimum Ground Clearance
(mm)
395
420
Engine
Model
YD4CZ70C1
YD4EZ80C1
YD4EZ90C1
Form
Electronic injection.vertical.water-cooled.four-stroke
Rated power(kW)
51.5
58.8
66.2
Fuel
Diesel
Rated power(r/min)
2400
Tarting method
Electric start
Steering Brake System
Steerig system type
Planetary differential steering
Brake system type
Wet friction steering
Drive System
Clutch type
Single-chip single-acting
Transmission type
Eight forward speed+ reverse gear
Transmission shift model
Gear shift
Walking System
Rack form
Rigid frame type
Track pitch section×number×width
90×51×400
90×56×400
The theoretical speed of each file(km/h)
Ahead:1.22;1.80;2.92; 3.84;5.50;8.08;13.13;17.25
Backward:0.97;1.43;2.32;3.04;4.36;6.41;10.42;13.68
Working Device
Lifter type
Semi-split
Tillage depth control
Force adjustment
PTO form
Type1,non-independent
Power output shaft speed(r/min)
720/1000
PTO shaft spline and the outer diameter mm
8×38
Model
NF-Q502
NF-Q602
NF-Q702
NF-Q802
Size
length×width×height(mm)
3430×1590×2300
Weight
(Kg)
1715
1890
1930
1990
Minimum Ground Clearance
(mm)
395
Engine
Model
YD4C50V1
YD4JZ60C1
YD4CZ70C1
YD4SZ80C1
Form
electronic injection.vertical.water-cooled.four-stroke
Rated power(kW)
36.8
44.1
51.5
58.8
Fuel
diesel
Rated speed(r/min)
2400
Starting method
Electric start
Steering Brake System
Steerig system type
Tooth embedded clutch-braking
brake system type
Wet friction type
Drive System
clutch type
Monolithic single-acting
transmission type
Main transmission (hydraulic stepless speed + mechanical gear)
+auxiliary transmission 2 files
transmission shift model
Gear shift
Walking System
rack form
Rigid frame type
track pitch section×number×width
90×46×350(with side teeth)
90×50×350(with side teeth)
the theoretical speed of each file(km/h)
Hydraulic:high0-9.2;low0-6.2
mechanical:8.2;5.3
Working Device
lifter type
Semi-split type
tillage depth control
Bit adjust(optional force adjust)
PTO form
Type1, non-independent
power output shaft speed(r/min)
620/960
PTO shaft spline and the outer diameter mm
8×38
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