With the rapid advancement of FPGA technology, Programmable System-on-Chip (SOPC) has emerged as a powerful embedded microprocessor system that combines the flexibility of FPGAs with the efficiency of SoC designs. SOPC systems are characterized by their hardware and software programmability, scalability, and upgradability, making them an attractive choice in modern embedded applications. At the core of SOPC lies the embedded microprocessor, which is implemented on the FPGA fabric. Xilinx offers several options for such cores, including the 32-bit soft-core MicroBlaze, the 32-bit PowerPC hard cores like PowerPC405 and PowerPC440, and ARM Cortex-A9. Altera also provides its Nios series of soft processors. This paper primarily focuses on the MicroBlaze soft core from Xilinx, exploring its architecture, design flow, and development tools, and applying it to build a compact, intelligent, and networked software radio platform in a real-world radio monitoring system.
**1. MicroBlaze Processor Structure**
The MicroBlaze soft-core processor is a configurable 32-bit RISC CPU optimized for use in Xilinx FPGAs. It allows designers to tailor the processor's configuration based on specific application needs. The MicroBlaze v7.1 version, currently the latest, features a wide range of customizable options. Key characteristics include:
- 32 general-purpose 32-bit registers
- 32-bit three-operand instruction format with two addressing modes
- Separate address and data buses for efficient data handling
- High-speed instruction and data cache with a 3- or 5-stage pipeline
- Flexible bus interface support, including LMB, OPB, PLB, XCL, FSL, and AXI
- Optional support for MMU, FPU, cache, exception handling, and debugging logic
These features make MicroBlaze highly versatile, enabling it to be used across a wide range of applications. Its internal architecture is illustrated in Figure 1.
Figure 1: MicroBlaze Processor Structure
The external interfaces of the MicroBlaze processor are defined as follows:
1. DPLB (Data Processor Local Bus), DOPB (Data On-chip Peripheral Bus): Data interface for communication between the processor and on-chip peripherals.
2. IPLB (Instruction Processor Local Bus), IOPB (Instruction On-chip Peripheral Bus): Instruction interface for fetching instructions.
3. DLMB (Data Local Memory Bus): High-speed data interface for direct memory access.
4. ILMB (Instruction Local Memory Bus): High-speed instruction interface for fast instruction retrieval.
5. MFSL0–15 (Main Fast Simple Link): Point-to-point data interface for FSL master devices.
6. SFSL0–15 (Slave Fast Simple Link): Point-to-point data interface for FSL slave devices.
7. IXCL (Instruction-side Xilinx CacheLink) and DXCL (Data-side Xilinx CacheLink): Interfaces for connecting to cache modules.
**2. EDK Tool Development Process**
Xilinx’s Embedded Development Kit (EDK) provides a comprehensive toolset for designing SOPC systems using both the MicroBlaze soft core and PowerPC hard processors. EDK includes tools such as Xilinx Platform Studio (XPS), the embedded system tool suite, IP cores, and the SDK. XPS offers a user-friendly interface for adding cores, configuring parameters, connecting buses, and generating MHS files. It also supports generating and modifying MSS files, managing projects, and visualizing system block diagrams.
A complete embedded system typically involves three main components: hardware construction, software and memory mapping, and application development. The hardware is built using Xilinx tools to create a flexible processing subsystem. EDK stores this information in MHS files. Software systems, including drivers and operating systems, are managed through MSS files, allowing multiple applications to run on the same platform.
The development process, as shown in Figure 2, outlines how hardware and software are integrated and deployed.
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