A Bode plot with three poles and one zero is used to analyze the gain and phase margins of a system. Assuming a DC gain of 80 dB, the first pole appears at 100 Hz, causing the gain curve to slope downward at -20 dB/decade. A zero located at 1 kHz causes the slope to flatten to 0 dB/decade, but the slope returns to -20 dB/decade after 10 kHz due to the second pole. The third and final pole at 100 kHz changes the gain slope to -40 dB/decade.
The unity gain frequency (where the gain crosses 0 dB) is at 1 MHz, which is often referred to as the loop bandwidth. The phase shift diagram illustrates how the placement of poles and zeros affects the feedback signal. The total phase shift is calculated based on the positions of these poles and zeros. The phase shift from a pole at any frequency (f) can be calculated as:
**Pole phase shift = -arctan(f/fp)**
Similarly, the phase shift from a zero at any frequency (f) is:
**Zero phase shift = -arctan(f/fz)**
To determine the stability of the loop, we only need to examine the phase shift at the 0 dB frequency (1 MHz). At this point, the first two poles and the zero cause the phase to shift from -180° to +90°, resulting in a net phase shift of -90°. The last pole introduces an additional phase shift of -84°, leading to a total phase shift of -174°, which results in a phase margin of just 6°. This small margin indicates that the loop may become unstable or even oscillate under certain conditions.
In NPN regulator compensation, the configuration of the conduction transistor involves shared electrodes, and common collector circuits are known for their low output impedance. This means that high-frequency poles appear in the loop gain curve. Since the NPN regulator lacks an inherent low-frequency pole, it uses dominant pole compensation, typically by integrating a capacitor within the IC to introduce a low-frequency pole.
The main pole (P1) of the NPN regulator is usually set at 100 Hz, reducing the gain slope to -20 dB/decade until the second pole (P2) at 3 MHz. At P2, the slope increases again by -20 dB/decade. The position of P2 depends on the power transistor and drive circuit, hence it is sometimes called the power pole. Since P2 occurs at a gain of -10 dB, its contribution to the phase shift at 1 MHz is minimal.
To assess stability, we calculate the phase margin at the 0 dB frequency. The first pole contributes -90°, while the second pole adds approximately -18°, resulting in a total phase shift of -108°. This gives a phase margin of 72°, indicating a very stable system. Although there are two poles, their high-frequency placement ensures that the phase shift remains well below the unstable threshold of -180°.
In LDO regulators, the PNP transistor is connected in a common emitter configuration, which has higher output impedance compared to the common collector setup. Low-frequency poles arise due to the load impedance and output capacitance. The frequency of the load pole (Pl) is given by:
**F(Pl) = 1/(2π × Rload × Cout)**
This makes it difficult to compensate the loop simply by adding a dominant pole. For example, consider a 5V/50mA LDO with Rload = 100 Ω and Cout = 10 μF. The load pole appears at 160 Hz. If a pole is added at 1 kHz internally, another pole (Ppwr) may appear at 500 kHz due to the PNP transistor and driver circuit.
With a DC gain of 80 dB, the system becomes unstable because the two low-frequency poles each contribute -90°, leading to a total phase shift of -180° at the 0 dB frequency (40 kHz). To stabilize the system, a zero must be introduced to counteract the negative phase shift. This zero, typically created by the ESR of the output capacitor, provides a +90° phase shift that cancels some of the effects of the low-frequency poles.
Using ESR for LDO compensation, the equivalent series resistance (ESR) of the output capacitor creates a zero in the loop gain. The zero frequency is determined by:
**Fzero = 1/(2π × Cout × ESR)**
For example, if Cout = 10 μF and ESR = 1 Ω, the zero occurs at 16 kHz. Adding this zero stabilizes the system by increasing the bandwidth and shifting the 0 dB intersection frequency from 30 kHz to 100 kHz. At 100 kHz, the zero contributes +81°, while the power pole at 500 kHz only adds -11°, resulting in a total phase shift of -110°. This gives a phase margin of 70°, confirming the system's stability. Thus, an output capacitor with the correct ESR value plays a crucial role in stabilizing an LDO regulator.
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