With the rapid advancement of FPGA technology, Programmable System-on-Chip (SOPC) has emerged as a powerful embedded microprocessor system that combines the benefits of SoC and FPGA. It offers hardware and software programmability, scalability, and upgradability, making it a promising direction in modern embedded systems. At the heart of SOPC lies an embedded microprocessor core implemented on an FPGA. Currently, several popular options are available, including Xilinx's 32-bit soft-core MicroBlaze, the 32-bit PowerPC series hard cores like PowerPC405 and PowerPC440, ARM Cortex-A9, and Altera's Nios series. This paper focuses on the MicroBlaze soft core from Xilinx, explaining its architecture, design flow, and development tools. It also demonstrates how this solution was applied in a real-world radio monitoring system to create a compact, intelligent, and networked software-defined radio platform.
**1. MicroBlaze Processor Architecture**
The MicroBlaze soft core is a configurable 32-bit RISC CPU optimized for Xilinx FPGAs. Designers can tailor its configuration based on specific project requirements, with various versions offering different features. Key characteristics of the MicroBlaze include:
- 32 general-purpose 32-bit registers
- A 32-bit three-operand instruction format with two addressing modes
- Separate 32-bit address and data buses
- High-speed instruction and data cache with a 3-stage or 5-stage pipeline
- Flexible bus architecture supporting LMB, OPB, PLB, XCL, and FSL interfaces, with newer versions adding AXI support
- Optional support for MMU, FPU, cache, exception handling, and debugging logic, which can be adjusted according to performance and area constraints
These features make MicroBlaze highly adaptable, expanding its application range. The current version, MicroBlaze v7.1, features an advanced internal architecture shown in Figure 1.
*Figure 1: MicroBlaze Processor Structure*
The external interfaces of the MicroBlaze processor include:
1. DPLB (Data Processor Local Bus), DOPB (Data On-Chip Peripheral Bus): Data interface for processor-local bus communication.
2. IPLB (Instruction Processor Local Bus), IOPB (Instruction On-Chip Peripheral Bus): Instruction interface for command fetching.
3. DLMB (Data Local Memory Bus): High-speed data interface for memory access.
4. ILMB (Instruction Local Memory Bus): High-speed instruction interface for program execution.
5. MFSL0–15 (Main Fast Simple Link): FSL master interface for point-to-point data transfer.
6. SFSL0–15 (Slave Fast Simple Link): FSL slave interface for direct communication.
7. IXCL (Instruction-side Xilinx CacheLink) and DXCL (Data-side Xilinx CacheLink): Interfaces for instruction and data caches.
**2. EDK Tool Development Process**
Xilinx’s Embedded Development Kit (EDK) provides a comprehensive toolset for designing SOPC systems using both MicroBlaze soft cores and PowerPC hard processors. EDK includes tools such as Xilinx Platform Studio (XPS), the embedded system tool suite, IP cores, and the SDK (Software Development Kit). XPS offers key features like:
- Adding and configuring cores, setting parameters, and connecting buses
- Generating and modifying MHS (Microprocessor Hardware Specification) files
- Supporting all underlying Xilinx tools and generating system block diagrams
- Enabling multi-user collaboration and project management
- Managing process flows and tool dependencies
A complete embedded system typically involves three main stages: hardware construction, software development and memory mapping, and application creation. The hardware is built using Xilinx technology to create a flexible processing subsystem, with MHS files storing the platform details. Software components, including drivers and OS, are defined in MSS (Microprocessor Software Specification) files, allowing multiple applications to run on the same platform. The development workflow is illustrated in Figure 2.
*Figure 2: EDK Embedded System Software and Hardware Development Process*
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