Xilinx Programmable Logic Device Design and Development (Basic) Serial 40: Spartan

2. Set the I/O assignment to be disabled.

Maximize [Package Pins], as shown in Figure 10-45, and cooperate with the button to complete the ordering of the device pins. In the figure, we put all the VREF pins together, select all VREF pins, and select the right button function. Set Prohibit], disables the allocation of all VREF pins.

Figure 10-45 Disabling Pin Assignment

Third, define compatible devices

In the FPGA design development phase, PlanAhead allows designers to define compatible chips, which can apply an I/O constraint to multiple FPGAs.
In the [Device] or [Package] window, select [Make Part CompaTIble...] in the right-click pop-up menu to select compatible devices. See Figure 10-46.

Figure 10-46 Specifying a compatible device

Fourth, import and analyze the I / O port list

PlanAhead can import files in many different formats for I/O pin planning. Before generating a comprehensive netlist, you can import files in CSV, UCF, and RTL format for analysis and distribution of I/O pins. However, it should be noted that when using this early I/O pin planning method, because there is no integrated netlist, the I/O allocation tool and the DRC verification tool do not know the relationship between the clock and each clock in the design. The details of high-speed logic are not clear, so the analysis is not complete. If possible, import the integrated netlist before performing I/O allocation.
Run the command [File] → [Import I/O Port...] → [From CSV...] to import the CSV format file. The CSV file directory is PlanAhead_Tutorial\Sources\IO_port_import.csv. Maximize the [I/O Ports] window, as shown in Figure 10-47, you can see the distribution of all Ports by default. Click the button next to the [I/O Ports] window to observe the changes in the port arrangement. The figure shows the common properties of each port.

Figure 10-47 [I/O Ports] window

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